VHDL - Projeto ComponenteNBits

Objetivo
Estudar uso de GENERIC e PROCESS


ComponenteNBits
Circuito Combinacional Com 3 entradas e 1 saída. Se comporta como a tabela que segue:

SEL S
00 a+b
01 a-b
10 a>>1
11 b>>1


Interface










ENTITY ComponenteNBits IS
GENERIC (N : INTEGER := 4);
PORT (a, b: IN STD_LOGIC_VECTOR (N-1 DOWNTO 0);
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
s: OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0));
END ComponenteNBits;


Arquivos

ComponenteNBits.vhd
http://www.4shared.com/file/k10UOjlw/ComponenteNBits.html


Simulação

force a 0000 0ns, 0101 20ns, 0100 40ns, 0000 60ns
force b 0001 0ns, 1100 20ns, 0010 40ns, 0000 60ns
force sel 00 0ns, 01 40ns, 10 60ns, 11 80ns
run 100ns

Links

http://www.eng.auburn.edu/~nelson/courses/elec5250_6250/VHDL%203%20Sequential.pdf
http://pldworld.biz/_hdl/2/esd.cs.ucr.edu/labs/tutorial/
http://vhdlguru.blogspot.com/